Flash memory with conformal floating gate and the method of making the same

ABSTRACT

A flash memory comprises a substrate having trenches formed therein. A tunneling oxide is formed on a surface of the substrate and adjacent to the trenches. A raised isolation fillers is formed in the trenches and protruding over an upper surface of the substrate, thereby forming a cavity between two adjacent raised isolation fillers. A floating gate is formed along a surface of the cavity to have a U-shaped structure in cross sectional view, wherein the high level of the U-shaped structure is the same with the one of the raised isolation fillers. An isolation structure is formed on the top of the raised isolation fillers and upper surface of the U-shaped structure. A dielectric layer is conformally formed on a surface of the floating gate and the isolation structure. A control gate is formed on the dielectric layer.

[0001] The present invention relates to a semiconductor device, and more specifically, to a flash memory having high coupling ratio and the method of fabricating the nonvolatile memory.

BACKGROUND OF THE INVENTION

[0002] The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Further, it can be used to replace magnetic disk memory. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMs.

[0003] Different types of devices have been developed for specific applications requirements in each of the segments of memory. In the device, electrical alterability is achieved by Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-thin dielectric interface and into the oxide conduction band. Typically, the thin dielectric layer is composed of silicon dioxide and the thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide and remain trapped there since the materials are high quality insulators. A conventional flash memory is a type of erasable programmable read-only memory (EPROM). One of the advantages of flash memory is its *capacity for block-by-block memory erasure. Furthermore, the speed of memory erasure is fast. For other EPROM, the memory erasure can take up to several minutes due to the erase mode of such type memory is done by bit-by-bit.

[0004] Various flash memories have been disclosed in the prior art, the type of the flash includes separated-gate and stacked-gate structure. U.S. Pat. No. 6,180,454 to Chang, et al, entitled “Method for forming flash memory devices”, and filed on Oct. 29, 1999. U.S. Pat. No. 5,956,268 disclosed a Nonvolatile memory structure. The prior art allows for array, block erase capabilities. U.S. Pat. No. 6,153,494 to Hsieh, et al., entitled “Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash” and filed on Feb. 11, 1998. The object of this invention is to provide a method of forming a stacked-gate flash memory having a shallow trench isolation with a high-step in order to increase the lateral coupling between the word line and the floating gate. Hsieh disclosed a step of forming nitride layer and then forming hallow trench isolation (STI) through the nitride layer into the substrate. Then, oxide is filled into the STI, the nitride is then removed leaving behind a deep opening about the filled STI. The detailed description may refer to the prior art. A stacked-gate flash memory cell is provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

[0005] Chen disclosed a nonvolatile memory with self-aligned floating gate in U.S. Pat. No. 6,140,182 and assigned to Actrans System Inc. A further prior art can be seen in U.S. Pat. No. 6,172,396 to Chang, the prior art provides a method that is capable of eliminating buried trenches in the source/drain regions without lowering the coupling rate between the floating gate and the control gate.

SUMMARY OF THE INVENTION

[0006] The object of the present invention is to form flash memory with higher coupling ratio.

[0007] It is another object of this invention to provide a method of forming a flash memory having sidewall coupling to increase the coupling ratio between the control gate and the floating gate of the cell.

[0008] The flash memory according to the present invention comprises a substrate having trenches formed therein. A tunneling oxide is formed on a surface of the substrate and adjacent to the trenches. A raised isolation fillers is formed in the trenches and protruding over an upper surface of the substrate, thereby forming a cavity between two adjacent raised isolation fillers. A floating gate is formed along a surface of the cavity to have a U-shaped structure in cross sectional view, wherein the high level of the U-shaped structure is the same with the one of the raised isolation fillers. An isolation structure is formed on the top of the raised isolation fillers and upper surface of the U-shaped structure. A dielectric layer conformally is formed on a surface of the floating gate and the isolation structure. A control gate is formed on the dielectric layer.

[0009] A method of manufacturing a flash memory comprises forming a first dielectric layer on a semiconductor substrate and patterning the first dielectric layer, the substrate to form trenches in the substrate. First isolations is refilled into the trenches, followed by removing the first dielectric layer, thereby forming a cavity between the first isolations and the isolations protruding over the substrate. A tunneling oxide is formed on the substrate, then a first conductive layer is formed on the tunneling oxide and along a surface of the first isolation. A second dielectric layer is formed on the first conductive layer. A portion of the second dielectric layer is removed to expose the first conductive layer on the first isolation. An oxidation is performed to transform the exposed first conductive layer into second oxide, thereby separating the first conductive layer. A third dielectric layer is formed on a surface of the first conductive layer. A second conductive layer is formed on the second dielectric layer as a control gate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0011]FIG. 1 is a cross section view of a semiconductor wafer illustrating the steps of forming isolation in a trench of a substrate according to the present invention.

[0012]FIG. 2 is a cross section view of a semiconductor wafer illustrating the steps of forming protruding isolation, tunneling oxide, first conductive layer according to the present invention.

[0013]FIG. 3 is a cross section views of a semiconductor wafer illustrating the step of performing a polishing according to the present invention.

[0014]FIG. 4 is a cross section views of a semiconductor wafer illustrating the step of forming a control gate according to the present invention.

[0015]FIG. 5 is a cross section view of a semiconductor wafer illustrating the steps of forming protruding isolation, tunneling oxide, first conductive layer according to the present invention.

[0016]FIG. 6 is a cross section view of a semiconductor wafer illustrating the steps of removing a second dielectric layer on the first conductive layer according to the present invention.

[0017]FIG. 7 is a cross section view of a semiconductor wafer illustrating the step of performing oxidation according to the present invention.

[0018]FIG. 8 is a cross section views of a semiconductor wafer illustrating the step of forming a control gate according to the present invention.

[0019] FIGS. 9-10 are a cross section views of a semiconductor wafer illustrating an alternative embodiment according to the present invention.

[0020]FIG. 11 is a cross section view of a semiconductor wafer illustrating the steps of removing a thin second dielectric layer on the first conductive layer according to the present invention.

[0021]FIG. 12 is a cross section view of a semiconductor wafer illustrating the step of performing oxidation according to the present invention.

[0022]FIG. 13 is a cross section view of a semiconductor wafer illustrating the steps of forming dielectric and control gate according to the present invention.

[0023]FIG. 14 is a cross section view of a semiconductor wafer illustrating the steps of forming dielectric and control gate after the removal of the oxide structure according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0024] The present invention proposes a novel structure and method to fabricate the stacked-gate flash memory. The flash memory cell includes a trench formed in a substrate 2, please refer to FIG. 3. A tunneling oxide 4 is formed on the surface of the substrate 2 and adjacent to the trench 6. A protruding isolation (filler) 8 is formed in the trench 6 and protruding over the upper surface of the substrate, thereby forming a cavity between the adjacent protruding isolation filler 8. A floating gate 14 is formed along the surface of the cavity 14 to have a U-shaped structure in cross sectional view. The high level of the U-shaped structure is the same with the one of the protruding isolation filler 8. A dielectric layer 16 is conformally formed on the surface of the floating gate 16 and a control gate 18 is formed on the dielectric layer 16. A second embodiment may refer to FIG. 6, the alternative case includes an isolation structure lying over the protruding isolation filler 8 and the upper surface of the U-shaped structure.

[0025] The method of forming the structure is described as follows. In first method, a trench is formed and a floating gate is formed in the trench to increase the coupling ratio. The detail description of the method will be seen as follows. In a preferred embodiment, as shown in the FIG. 1, a single crystal silicon substrate 2 with a <100> or <111> crystallographic orientation is provided. A masking layer 4 such as silicon nitride layer 4 is formed on the substrate 2. Typically, The silicon nitride layer 8 is deposited by any suitable process. For example, Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhance Chemical Vapor Deposition (PECVD), High Density Plasma Chemical Vapor Deposition (HDPCVD). In the preferred embodiment, the reaction gases of the step to form silicon nitride layer include SiH₄, NH₃, N₂ or SiH₂Cl₂, NH₃, N₂. The thickness of the masking layer 4 is about 500-3500 angstroms.

[0026] Next, as can be seen by reference to FIG. 1, a photoresist (not shown) is patterned on the masking layer 4 to define trench region, followed by etching the masking layer and substrate 2 to form trenches 6 in the substrate 2. The photoresist is next removed by oxygen plasma ashing. Subsequently, the trench 10 is filled with isolation oxide 8, using the method of high density plasma (HDP) deposition or LPCVD. Next, the substrate 2 is subjected to chemical-mechanical polishing (CMP), thus forming shallow trench isolation (STI) 8 as shown in FIG. 1. Then, the masking layer 4 is removed by hot phosphorus acid solution, thereby forming protruding isolation filler 8 protruding over the surface the substrate 2. A cavity 10 is therefore formed between the raised isolation filler 8. The step high of the protruding isolation filler 8 can be defined by the thickness of the masking layer 4. Hence, the coupling ratio can be controlled by the present invention.

[0027] Next, tunneling oxide 12 is formed on the surface of the substrate by thermal oxidation or CVD. A conductive layer 14 such as in-situ doped polysilicon along the surface of the cavity 10 and the protruding isolation filler 8. The conductive layer 14 is chosen from doped polysilicon or in-situ doped polysilicon, silicon or amorphous silicon.

[0028] This is achieved preferably through a LPCVD method employing silane as a silicon source material at a temperature range between about 500 to 650 degree C. A chemical mechanical polishing (CMP) is employed to remove the upper surface of the conductive layer 14 to expose the surface of the protruding isolation filler 8, thereby separating each cell, as shown in FIG. 3.

[0029] The remained polysilicon layer 14 serve as a floating gate and isolated by the protruding isolation filler 8. As another key aspect of the present invention, remained thin polysilicon layer 14 is conformally formed so as to follow the contours of the cavity 10, thus providing additional surface to the control gate dielectric that is to be formed later. In another words, the polysilicon should not fill the totally the cavity 10.

[0030] An interpoly dielectric layer 16 is next formed over the contours of the conformal floating gate and the upper surface of the protruding isolation filler 8, as shown in FIG. 4. It is preferred that the interpoly dielectric layer 16 comprises but not limited to oxide/nitride/oxide (ONO), ON. Then, a further polysilicon layer 18 is formed over the interpoly dielectric layer 16 to act as the control gate and word line. Thus, a flash is formed as shown in the cross-sectional view of FIG. 4. A further patterning may be used to define the control gate. The control gate can be chosen from polysilicon, silicon or amorphous silicon.

[0031] The higher coupling can be obtained due to the floating gate formed against the high-step oxide protruding over the isolation trench of the present invention.

[0032] Please referring to FIG. 5, a second embodiment according to the present invention is similar to the first embodiment, any suitable dielectric layer 16 is deposited on the first conductive layer 14 after the first conductive layer 14 is formed. The material for the layer 16 can be any suitable material such as nitride, oxide or spin-on-glass. A further embodiment can be seen in FIG. 10, the dielectric layer 16 a is a thin conformal oxidation resistant layer 16 a that is conformally formed along the surface of underlying structure. The thickness of the first conductive layer 14 and the oxidation resistant layer 16 are respectively 100-1000 angstroms and 50-500 angstroms. The oxidation resistant layer 16 can be silicon nitride. The benefit of the thin conformal oxidation resistant layer 16 a to the method is a thinner layer is needed for saving the cost.

[0033] Turning to FIG. 6 and FIG. 11, a CMP is introduced to polish the dielectric layer 16 or the oxidation resistant layer 16 a to expose the portion of the first conductive layer 14 lying on the protruding isolation 8. An oxidation is performed in oxygen ambient to oxidize the first conductive layer 14 into oxide. Preferably, the first conductive layer 14 is formed of polysilicon. It has to be noted that the step may separate the polysilicon layer and define the floating gate by maskless step as shown in FIG. 8 and FIG. 12. Then, the dielectric layer 16 or the oxidation resistant layer 16 a is removed. The following sequences are similar to the aforementioned embodiment to deposit the ONO 20 and the control gate 22.

[0034] Another embodiment according to the present invention is to remove the oxide 18 prior to forming the ONO 20 and control gate 22. The results are respectively formed in FIG. 9 and FIG. 14. The protruding oxide 8 is recessed due to the removal of the oxide 18, thereby increasing the sidewall surface. Thus, under such structure, the protruding oxide 8 is protruding over the substrate and the U-shaped floating gate 14 is also protruding over the protruding oxide 8, as shown in FIG. 14, 9. The coupling ratio may be increased by the structure.

[0035] As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention is illustrative of the present invention rather than limiting the present invention. Having described the invention in connection with a preferred embodiment, modification will now suggest itself to those skilled in the art. Thus, the invention is not to be limited to this embodiment, but rather the invention is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

[0036] While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

APPENDIX A

[0037] William E. Alford, Reg. No. 37,764; Farzad E. Amini, Reg. No. P42,261; Aloysius T. C. AuYeung, Reg. No. 35,432; William Thomas Babbitt, Reg. No. 39,591; Carol F. Barry, Reg. No. 41,600; Jordan Michael Becker, Reg. No. 39,602; Bradley J. Bereznak, Reg. No. 33,474; Michael A. Bernadicou, Reg. No. 35,934; Roger W. Blakely, r., Reg. No. 25,831; Gregory D. Caldwell, Reg. No. 39,926; Ronald C. Card, Reg. No. P44,587; Thomas M. Coester, Reg. No. 39,637; Stephen M. De Klerk, under 37 C.F.R. § 10.9(b); Michael Anthony DeSanctis, Reg. No. 39,957; Daniel M. DeVos, Reg. No. 37,813; Robert Andrew Diehl, Reg. No. 40,992; Matthew C. Fagan, Reg. No. 37,542; Tarek N. Fahmi, Reg. No. 41,402; James Y. Go, Reg. No. 40,621; James A. Henry, Reg. No. 41,064; Willmore F. Holbrow III, Reg. No. P41,845; Sheryl Sue Holloway, Reg. No. 37,850; George W Hoover II, Reg. o. 32,992; Eric . yman, Reg. No. 30,139; Dag H. Johansen, Reg. No. 36,172; William W. Kidd, Reg. No. 31,772; Erica W. Kuo, Reg. No. 42,775; Michael J. Mallie, Reg. No. 36,591; Andre L. Marais, under 37 C.F.R. § 10.9(b); Paul A. Mendonsa, Reg. No. 42,879; Darren J. Milliken, Reg. 42,004; Lisa A. Norris, Reg. No. P44,976; Chun M. Ng, Reg. No. 36,878; Thien T. Nguyen, Reg. No. 43,835; Thinh V. Nguyen, Reg. No. 42,034; Dennis A. Nicholls, Reg. No. 42,036; Kimberley G. Nobles, Reg. No. 38,255; Daniel E. Ovanezian, Reg. No. 41,236; Babak Redjaian, Reg. No. 42,096; William F. Ryann, Reg. 44,313; James H. Salter, Reg. No. 35,668; William W. Schaal, Reg. No. 39,018; James . cheller, Reg. No. 31,195; Jeffrey Sam Smith, Reg. No. 39,377; Maria McCormack Sobrino, Reg. No. 31,639; Stanley . Sokoloff, Reg. No. 25,128; Judith A. Szepesi, Reg. No. 39,393; Vincent P. Tassinari, Reg. No. 42,179; Edwin . Taylor, Reg. No. 25,129; John F. Travis, Reg. No. 43,203; George G. C. Tseng, Reg. No. 41,355; Joseph A. Twarowski, Reg. No. 42,191; Lester J. Vincent, Reg. No. 31,460; Glenn E. Von Tersch, Reg. No. 41,364; John Patrick ard, Reg. o. 40,216; Charles T. J. Weigell, Reg. No. 43,398; Kirk D. Williams, Reg. No. 42,229; James M. Wu, Reg. No. P45,241; Steven D. Yates, Reg. No. 42,242; Ben J. Yorks, Reg. No. 33,609; and Norman Zafman, Reg. No. 26,250; my patent attorneys, and Andrew C. Chen, Reg. No. 43,544; Justin M. Dillon, Reg. No. 42,486; Paramita Ghosh, Reg. No. 42,806; and Sang Hui Kim, Reg. No. 40,450; my patent agents, of BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP, with offices located at 12400 Wilshire Boulevard, 7th Floor, Los ngeles, Calif. 90025, telephone (310) 207-3800, and James R. Thein, Reg. No. 31,710, my patent attorney.

APPENDIX B Title 37, Code of Federal Regulations, Section 1.56 Duty to Disclose Information Material to Patentability

[0038] (a) A patent by its very nature is affected with a public interest. The public interest is best served, and the most effective patent examination occurs when, at the time an application is being examined, the Office is aware of and evaluates the teachings of all information material to patentability. Each individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability as defined in this section. The duty to disclosure information exists with respect to each pending claim until the claim is cancelled or withdrawn from consideration, or the application becomes abandoned. Information material to the patentability of a claim that is cancelled or withdrawn from consideration need not be submitted if the information is not material to the patentability of any claim remaining under consideration in the application. There is no duty to submit information which is not material to the patentability of any existing claim. The duty to disclosure all information known to be material to patentability is deemed to be satisfied if all information known to be material to patentability of any claim issued in a patent was cited by the Office or submitted to the Office in the manner prescribed by 1.97(b)-(d) and 1.98. However, no patent will be granted on an application in connection with which fraud on the Office was practiced or attempted or the duty of disclosure was violated through bad faith or intentional misconduct. The Office encourages applicants to carefully examine:

[0039] (1) Prior art cited in search reports of a foreign patent office in a counterpart application, and

[0040] (2) The closest information over which individuals associated with the filing or prosecution of a patent application believe any pending claim patentably defines, to make sure that any material information contained therein is disclosed to the Office.

[0041] (b) Under this section, information is material to patentability when it is not cumulative to information already of record or being made or record in the application, and

[0042] (1) It establishes, by itself or in combination with other information, a prima facie case of unpatentability of a claim; or

[0043] (2) It refutes, or is inconsistent with, a position the applicant takes in:

[0044] (i) Opposing an argument of unpatentability relied on by the Office, or

[0045] (ii) Asserting an argument of patentability.

[0046] A prima facie case of unpatentability is established when the information compels a conclusion that a claim is unpatentable under the preponderance of evidence, burden-of-proof standard, giving each term in the claim its broadest reasonable construction consistent with the specification, and before any consideration is given to evidence which may be submitted in an attempt to establish a contrary conclusion of patentability.

[0047] (c) Individuals associated with the filing or prosecution of a patent application within the meaning of this section are:

[0048] (1) Each inventor named in the application;

[0049] (2) Each attorney or agent who prepares or prosecutes the application; and

[0050] (3) Every other person who is substantively involved in the preparation or prosecution of the application and who is associated with the inventor, with the assignee or with anyone to whom there is an obligation to assign the application.

[0051] (d) Individuals other than the attorney, agent or inventor may comply with this section by disclosing information to the attorney, agent, or inventor. 

What is claimed is:
 1. A flash memory comprising: a substrate having trenches formed therein; a tunneling oxide formed on a surface of said substrate and adjacent to said trenches; raised isolation fillers formed in said trenches and protruding over an upper surface of said substrate, thereby forming a cavity between two adjacent raised isolation fillers; a floating gate formed along a surface of said cavity to have a U-shaped structure in cross sectional view, wherein the high level of said U-shaped structure is the same with the one of said raised isolation fillers; an isolation structure formed on the top of said raised isolation fillers and upper surface of said U-shaped structure; a dielectric layer conformally formed on a surface of said floating gate and said isolation structure; and a control gate formed on said dielectric layer.
 2. The flash memory of claim 1, wherein said raised isolation filler includes oxide.
 3. The flash memory of claim 1, wherein said floating gate includes polysilicon, silicon or amorphous silicon.
 4. The flash memory of claim 1, wherein said control gate includes polysilicon, silicon or amorphous silicon.
 5. The flash memory of claim 1, wherein said dielectric layer includes oxide/nitride/oxide.
 6. The flash memory of claim 1, wherein said dielectric layer includes oxide/nitride.
 7. A flash memory comprising: a substrate having trenches formed therein; a tunneling oxide formed on a surface of said substrate and adjacent to said trenches; raised isolation fillers formed in said trenches and protruding over an upper surface of said substrate, thereby forming a cavity between two adjacent raised isolation fillers; a floating gate formed along a surface of said cavity to have a U-shaped structure in cross sectional view, wherein the high level of said U-shaped structure is higher than the one of said raised isolation fillers, thereby protruding over said raised isolation fillers to increase a coupling ratio; a dielectric layer conformally formed on a surface of said floating gate and said raised isolation fillers; and a control gate formed on said dielectric layer.
 8. The flash memory of claim 7, wherein said raised isolation filler includes oxide.
 9. The flash memory of claim 7, wherein said floating gate includes polysilicon, silicon or amorphous silicon.
 10. The flash memory of claim 7, wherein said control gate includes polysilicon, silicon or amorphous silicon.
 11. The flash memory of claim 7, wherein said dielectric layer includes oxide/nitride/oxide.
 12. The flash memory of claim 7, wherein said dielectric layer includes oxide/nitride.
 13. A method of manufacturing a flash memory, comprising: forming a first dielectric layer on a semiconductor substrate; patterning said first dielectric layer, said substrate to form trenches in said substrate; forming isolations into said trenches; removing said first dielectric layer, thereby forming a cavity between said isolations and said isolations protruding over said substrate; forming tunneling oxide on said substrate; forming a first conductive layer on said tunneling oxide and along a surface of said isolation; removing a portion of said first conductive layer to a surface of said isolation, wherein said first conductive layer act as a floating gate; forming a second dielectric layer on a surface of said floating gate; and forming a second conductive layer on said second dielectric layer as a control gate.
 14. The method of claim 13, wherein said first dielectric layer comprises nitride.
 15. The method of claim 13, wherein said first dielectric layer is removed by hot phosphorus acid solution.
 16. The method of claim 13, wherein said first conductive layer is removed by chemical mechanical polishing.
 17. The method of claim 13, wherein said second dielectric layer comprises oxide/nitride.
 18. The method of claim 13, wherein said second dielectric layer comprises oxide/nitride/oxide.
 19. A method of manufacturing a flash memory, comprising: forming a first dielectric layer on a semiconductor substrate; patterning said first dielectric layer, said substrate to form trenches in said substrate; forming first isolations into said trenches; removing said first dielectric layer, thereby forming a cavity between said first isolations and said first isolations protruding over said substrate; forming a tunneling oxide on said substrate; forming a first conductive layer on said tunneling oxide and along a surface of said first isolation; forming a second dielectric layer on said first conductive layer; removing a portion of said second dielectric layer to expose said first conductive layer on said first isolation; performing an oxidation to transform said exposed first conductive layer into second isolation, thereby separating said first conductive layer; removing said second dielectric layer; forming a third dielectric layer on a surface of said first conductive layer; and forming a second conductive layer on said second dielectric layer as a control gate.
 20. The method of claim 19, wherein said second dielectric layer includes oxide, nitride or SOG. 21.The method of claim 19, wherein said second dielectric layer includes oxidation resistant layer that is conformally formed on said first conductive layer.
 22. The method of claim 19, further comprising removing said second isolation while removing said second dielectric layer.
 23. The method of claim 19, wherein said first dielectric layer comprises nitride.
 24. The method of claim 23, wherein said first dielectric layer is removed by hot phosphorus acid solution.
 25. The method of claim 19, wherein said first conductive layer is removed by chemical mechanical polishing.
 26. The method of claim 19, wherein said third dielectric layer comprises oxide/nitride.
 27. The method of claim 19, wherein said third dielectric layer comprises oxide/nitride/oxide. 